Abstract:
In recent years, the proliferation of the Internet of Things (IoT) has led to a major increase in the quantity and type of devices involved in digital communications. Various Lightweight Cryptography (LWC) algorithms have been proposed to answer the need of cryptography in constrained devices. Although using separate algorithms for products with varying capacities is advantageous for optimization, it creates the risk that a single product may need to support multiple cryptographic primitives. This thesis aims to find an efficient way of providing hardware acceleration for multiple cryptography algorithms in lightweight System-on-Chips (SoC). For this pur pose, we present a design methodology that identifies the common portions across LWC algorithms and uses them to increase shared resources in the hardware. We explore two approaches to accelerator design: A fully-hardware approach and a hardware- software approach. Our observations indicate that the second approach, which employs an accelerator with a custom ISA, is more effective when designing for versatility. We leverage the open-source PicoRV32 processor to construct a lightweight SoC which employs various accelerators supporting Ascon, TinyJAMBU, and PHOTON Beetle LWC algorithms. To enable multi-algorithm support, we utilize hardware multi plexing of unshared resources, as well as Dynamic Partial Self-Reconfiguration (DPSR) on FPGA. These implementations are compared with each other and with dedicated ac celerators in terms of energy efficiency, area, and throughput. The associated tradeoffs and the conditions in which each variant is useful are determined.
