Abstract:
Low density parity check (LDPC) codes are linear block codes used for error correction mostly in high speed digital communication systems like digital broadcasting, optical fiber communications and wireless local area networks. LDPC codes have been subject to extensive research because of their significant performance in error correction. LDPC codes are mainly decoded using an iterative algorithm called sum product algorithm. This algorithm can be implemented in both probability and log domains. Since it is more suitable for hardware, sum product algorithm is commonly implemented in logdomain. The work done in this MS thesis is hardware implementation of LDPC decoders for variations of sum product algorithm in log-domain. Irregular LDPC codes which were found to be better in error correction were used in all implementations. Decoders were designed configurable for usage of different parity check matrices. All decoders were implemented using parallel architecture and one of the variations of the algorithm was also implemented using serial and semi-parallel architectures. Decoders were implemented in VHDL (VHSIC Hardware Description Language). Functional verification was made by running simulations, using Cadence NCSIM simulator, a top-level VHDL testbench and input stimuli generated using MATLAB. As the result of the simulations, bit error rate (BER) values for different signal to noise ratio (SNR) values were found for each decoder implementation. The implementations were synthesized to logic gates in 65 nm technology. Area reports were generated using the synthesis tool, Synopsys Design Compiler. Finally, the power estimation was done for each decoder implementation using Synopsys Power Compiler tool. As the result of the analysis, the decoder implementations are compared according to their BER performance, area and power consumption.
