Abstract:
This thesis covers realization and modeling of novel water-gated field effect transistors (WG-FETs) which use 16-nm-thick single crystalline silicon lm as active layer. WG-FET devices utilize electrical double layer (EDL) structure as a replacement of gate insulator and operate in the non-Faradaic region (under 1 V) without causing any oxidation/reduction reactions. Performance parameters based on voltage distribution on EDL are extracted and current-voltage relations are modeled. Various WG-FET devices with both probe- and planar-gate setups are simulated, fabricated and tested. E ects of gate distance, gate topology, eld and source/drain electrode insulation on transistor performance are investigated. Best ON=OFF ratios are measured with probe-gate devices for both insulated and uninsulated source/drain electrodes. Performance of probe-gate devices with uninsulated source/drain electrodes are superior to the ones with insulated source/drain due to absence of parasitic resistances related with the overlapping area of insulation layer. Planar-gate devices with source/drain insulation have lower ON=OFF ratios compared to probe-gate counterparts and device performance tends to deteriorate with increasing gate distance. Without source/drain electrode insulation, proper transistor operation is not obtained with planar-gate devices. Measurement results are in agreement with theoretical models. Inverters and ring oscillators are realized as circuit applications. WG-FET is a promising device platform for micro uidic applications where sensors and read-out circuits can be integrated at transistor level.
