Abstract:
Sigma delta analog to digital conversion is an effective way of converting analog signals to digital signals when high signal to noise ratio and low power consumption is needed. Instead of comparing the input signal with references, the sum of differences of the signal between each comparison is compared differentially or with references. This operation could be achieved with integrators and a transfer function in s or z-domain. When this comparison is performed more frequently than the Nyquist rate of the signal which is called oversampling, less quantization error is obtained. Thus, high signal to noise ratio and less harmonics in the system is obtained. Due to increase in mobile systems, power consumption became an important issue. Hence, engineers are more focused of efficiency of the systems. In this thesis, methods about designing low power sigma delta analog to digital converters with high performance are studied. Initially, 2nd order conventional and feed-forward discrete time sigma delta analog to digital converters with single-bit and multi-bit quantizers are studied. Next, 3rd order discrete time and 2-1 multi-stage sigma delta analog to digital converters are investigated. Afterwards, continuous time sigma delta conversion with different type of integrators is studied. Furthermore, a hybrid structure containing both discrete and continuous time integrators is investigated. In the meantime, the layout of the designs are prepared. Performance results of all the designs are obtained with post-layout simulations as well as the test results of the produced integrated circuits. Post-layout simulations show that the performance of the designs are close to the results of the designs with best results in the literature.
