Abstract:
System-on-a-chip solutions require hardware based integrated circuit (IC) random number generator (RNG) for trustworthy transmission of information. Fully digital gate based IC RNGs became popular because of their uncomplicated integration to digital platforms. RNGs based on ring oscillators (ROs) are the most well-known and widely used type among various digital gate based RNGs. Existing works on generating random bits by ROs mostly do not have detailed analysis on phase noise and jitter which are the entropy source of an RNG. This thesis analyzes the suitability of existing ROs for random number generation and possible improvements in order to increase the randomness of an RO. Three main contributions are presented. The rst main contribution of this thesis to RNG is investigating the possibility of weak inversion operation of complementary metal oxide semiconductor (CMOS) transistors in order to maximize the randomness of CMOS RO used in RNG. In order to predict the weak inversion noise performance of an RO, phase noise and jitter models of a CMOS RO in weak inversion operating region are obtained. These models ll a missing point in the literature and introduce the phase noise and jitter models of RO in weak inversion. This is the second main contribution of this thesis. Despite the consensus on the positive e ects of white noise for random number generation, the e ects of icker noise on randomness are insu ciently investigated. Finally, the third main contribution of this thesis in terms of RNG is investigating the e ects of icker noise in order to address its usefulness for random number generation.
