Abstract:
In this thesis, design aspects of discrete time chaos based cryptographic grade TRNGs are studied starting from chaotic map equations to in depth analyses of the generated entropy. Custom mathematical models of discrete time chaos based TRNGs are developed to predict the randomness performance ahead of the physical implementation. A practical information measure, T-entropy, is used to characterize the entropy capacity of discrete time chaos based TRNGs, since conventional statistical tests can only provide pass/fail type binary outputs. Maximum allowable parameter variation boundaries for hardware design are determined using T-entropy calculations. A new dual entropy core TRNG architecture is introduced along with its mathematical model. The superiority of the proposed architecture over conventional single entropy core TRNG architecture is presented through a comparative study of generated entropy, and its sensitivity to parameter variations. A proof of concept novel dual entropy core discrete time chaos based TRNG circuit is implemented on a recon gurable analog platform, and measurement results are presented. A novel integrated dual entropy core discrete time chaos based TRNG circuit is designed, and implemented in 180nm CMOS technology using a new, matching driven design methodology, and the measurement results of the prototype chip are presented.
