Abstract:
High performance analog circuits need to be modified according to modern telecommunication needs such as higher frequency (GHz regions), low power, low voltage, low noise and higher relative dynamic range. The attractive attributes of current mode approaches such as higher speed, greater linearity, larger bandwidth, etc., made them very popular in the design of high performance analog circuits. The second generation current conveyor (CCII) is the most widely used active element in high performance current mode design. In this work, new high performance, low noise CMOS CCII circuit implementations are proposed. The first implementation, which is based on differential pairs, has high voltage swings on ports X and Y, very small equivalent impedance on port X, high equivalent impedances on ports Y and Z and also high-valued voltage and current transfer bandwidths. The second CCII implementation, which replaces the source follower transistors of the first implementation with super source follower ones, has very small equivalent impedance on port X, higher voltage and current transfer bandwidths compared to the first implementation. The final implementation is a self biased one which uses no additional biasing voltage or current sources other than the two supply rails. The proposed circuits are laid-out using Mentor Graphics IC Station Layout Editor and post layout simulations are performed with HSpice using AMS 0.35μm technology parameters. In addition, a common noise model of the proposed circuits is obtained which is composed of an input referred noise voltage source at high impedance port Y and an input referred noise current source at low impedance port X. The noise values are optimized by adjusting the gm values of the transistors. Furthermore, the noise reduction techniques are tested on both current mode and voltage mode filter circuits. Considerable noise reductions are obtained especially for high order filter circuits.
