Abstract:
Improvements in fabrication processes have enabled designers to bene t from sub-micron devices, which have led to the integration of multibillion transistors. However, circuit complexity increases together with the silicon complexity, since the e ect of process variations in sub micron technologies are drastically increased. Thus, design automation tools have emerged to reduce design time without sacri cing performances. To achieve that goal, simulation based optimization algorithms for analog circuit circuits are developed in this thesis. In order to synthesize a robust circuit, yield is de ned as a new design objective, which is tried to be maximized during the optimization process. To enhance the e ciency of yield estimation, Quasi-Monte Carlo (QMC) method, has been utilized in optimization. In addition, since QMC is deterministic and has no natural variance, there is no convenient way to obtain error bounds for the estimation. To determine the con dence interval of the estimated yield, scrambled-QMC method and conventional QMC method are combined. Therefore, a hybrid method is proposed, where a single QMC is performed to determine infeasible solutions in terms of yield, which is followed by a few scrambled QMC analyses providing variance and con dence interval of the estimated yield. In addition to the variation-aware tools, a layout-aware tool is proposed, in which a simulation-based circuit sizing tool with a template based layout generation tool are combined. The layout-induced parasitics are automatically extracted and are taken into account during the optimization process. To reduce the run time cost due to parasitic extraction, a two step methodology is developed. Finally, the circuits obtained at the end of optimization are implemented as an integrated circuit to show the e ectiveness of the algorithms.
