Abstract:
In this study, a front-end circuitry is designed for a 3 Tesla Magnetic Resonance Imager Receiver with UMC 0.18 m technology. Folded cascode topology is seemed to be the optimum design for our design speci cations which are 1.2 V supply voltage, <2 mW power consumption and <1 dB NF. For the designed fully di erential folded cascode low-noise ampli ers (FDFC LNAs), layouts are drawn and the layout of the FDFC LNA with NMOS input pair is sent to fabrication. For FDFC LNA with NMOS input pair; 54 dB voltage gain, 34 dB power gain is obtained. A noise gure of 0.4 dB in schematic simulations, 0.7 dB in post-layout simulations is measured. For FDFC LNA with PMOS input pair; 57.5 dB voltage gain, 36.5 dB power gain is obtained. A noise gure of 0.5 dB in schematic simulations, 0.8 dB in post-layout simulations is measured. Both LNAs have power consumption of 1.7 mW. During this study, LNA topologies are observed and compared. Detailed analysis of circuits is done and simulated results are observed to be matching with the mathematical expressions around 93%. Consequently; design of an LNA with low-voltage and low-power requirements heavily depends on the overall system, which means there is not an optimum design way satisfying all of the speci cations. Designer should chose one of the best circuit topology which meets most of the application demands, that is folded cascode topology for our case.
