Abstract:
Sigma-delta analog digital converter ( ADC) is widely used for high resolution applications such as audio applications. Sigma-delta ADC uses the oversampling process; therefore, it can reach high resolutions. Decimation process downsamples the sampling frequency and eliminates the redundant data which are generated by the oversampling process. The digital part of the sigma-delta ADC contains decimation and low-pass filters. Digital low-pass filter attenuates the noise which is pushed out of band by the oversampling process. Digital filters perform arithmetic calculations. Thus, they consume power. Low power design of decimation filter is an important issue for achieving a low power sigma-delta ADC. In this thesis, a low power decimation filter for sigma-delta ADC for audio frequency is implemented. In order to achieve this goal, multistage decimation filter architecture is used. The decimation filter consists of a third order Cascaded Integrator Comb (CIC) filter, one half-band filter and one Finite Impulse Response (FIR) filter. In this design, input signal bandwidth is 20 KHz and sampling frequency is 2.5 MHz. Half-band and FIR filter coefficients are generated using Parks McCellan algorithm. Multiplierless filter design is used for achieving low power consumption. Filter coefficients are represented by Canonical Signed Digit (CSD) representation. Horizontal Super Subexpression Elimination (HSSE) method is applied to CSD coefficients. In addition, half-band and FIR filters are designed using GAM algorithm which is proposed by Mustafa Aktan to compare manual and CAD design results. GAM algorithm reduces the number of signed power of two (SPT) terms in the coefficients while keeping the quantization word length as small as possible. Common Subexpression Elimination (CSE) method is applied to the filter coefficients by the GAM algorithm. All filters are designed with VHDL and implemented in 0.35μm CMOS process. The power consumption is measured for different supply voltage values. For 3.3V supply, 2.2 mW; for 2.5V supply, 1.1mW; and for 1.2V, 204 μW is dissipated for manual design of the decimation filter. Furthermore, for 3.3V supply, 1.7 mW; for 2.5V supply, 859 μW; and for 1.2V, 159 μW is dissipated for the decimation filter designed using GAM algorithm.
