Abstract:
As the complexity of on-chip systems grows, scalability and re-configurability becomes an important issue in both system and interconnection levels for SoC systems. Flexible and configurable architectures bring the advantage of reusability of the same hardware in different regular topologies such as torus, mesh, tree and in custom irregular ones. Research in NoC design points the importance of scalability, configurability and flexibility of the routers and on chip interconnects. This thesis describes an adaptive and flexible router design for all Network on Chip topologies, which can be changed during runtime. In °exible NoCs, table updates are carried out by a central unit, which increases complexity and area of the overall system. In AFRONOC, a re-duced form of the link state routing is introduced for table updates so that the overall system can set up/change the topology by itself. Hence, the proposed adaptation algorithm makes the router stand-alone, that means it can adapt to the rest of the network without help of any external or central monitoring. The proposed adaptation process initializes the routing tables in a short time when compared with the reconfiguration based methods. Design-time configurability is achieved in terms of the number of channels, the number of nodes in the network, buffer size of each channel and physical data width. As a result, the router can be considered as a solution in ad-hoc NoCs for fast prototyping, which is necessary for filling the design productivity gap in NoC design. Area occupation of an example implementation with four I/O channels, eight bit data width, four bit address width on a Virtex-II pro xcvp70 device is 750 slice, which is 2 per cent of the total area of the FPGA.
