Abstract:
Sigma delta analog digital converters which are widely used in electronics are gradually achieving faster speeds and lower power consumption. The most important factor that affects speed and power consumption is the type of the sigma delta analog digital converter. To achieve higher speed, using continuous time design instead of discrete time design is more reasonable. The other factor that affects the performance of the sigma delta analog to digital converter is the mode of the design which is current mode or voltage mode. Current mode design has a lot of advantages against voltage mode design but there are a few disadvantages of the current mode design when the resolution of the sigma delta analog digital converter increases. First of all, in this thesis, there is a summary of a one bit 4th order continuous time current mode sigma delta analog digital converter with 128 MHz sampling frequency and 32 MHz operating frequency which was designed before. Also, the test of the same structure is included. Moreover, upgrading the structure from one bit to three bit and the test of the new structure are explained. Hence, a three bit 4th order continuous time current mode sigma delta analog digital converter with 128 MHz sampling frequency and 32 MHz operating frequency is presented.
