3.125Gbps FIR equalizer implementation in 65nm CMOS technology

Abstract

This thesis describes channel degradation in a basic telecommunication system with its sources (crostalk and metalic channel los) and results (inter-symbol interference). Compensation of this channel degradation via methodology caled equalization is focused on. Adaptive equalization techniques such as zero forcing, least mean squares (LMS), recursive least squares (RLS) and constant modulus algorithm (CMA) are theoreticaly explained and LMS and RLS are supported with regarding MATLAB Simulink simulations using 30inch PCB trace model as the channel model. Comparison of adaptation algorithms, equalization cost functions and tap spacing of tapped delay line in using 30inch PCB trace model as the channel model. Comparison of adaptation algorithms, equalization cost functions and tap spacing of tapped delay line in FIR equalizer in Simulink are also held for this thesis. Coeficients obtained from Simulink environment are used to verify performance of FIR equalizer designed in STMicroelectronics CMOS065 (65nm) technology for 3.125Gbps data rate. Building blocks of FIR equalizer are analyzed in detail and design limitations are summarized. Simulations showed that closed eye at the receiver after 30inch PCB channel, can be cleaned up to data eye with 28ps jiter by means of 4-tap FIR equalizer with T/8 tap spacing operating at 1.2V power supply, 3.125Gbps data rate and at the expense of only 13mA of current consumption.