Abstract:
Automatic analog design tools are very attractive for the integrated circuit (IC) providers, because they increase the employees' efficiency and productivity; eliminate the high time and effort consumption. A performance evaluator is needed to spend no time for optimization of the unfeasible circuits and circuits which can not meet specifications.The work in this thesis is part of a complete analog design automation system from top level to the lowest level of synthesis. The work concentrates on analog circuits built with CMOS (Complementary Metal Oxide Semiconductor) transistors which are the current and future trend of analog circuit design. Partitioning of the problem to simpler sub problems is the major strategy used. General design equations valid for all analog systems are used to model the sub-blocks. Design equations of the sub blocks are arranged according to the sub block type and the succeeding block. Finally equations are found relating design specifications to the design parameters.The system has been realized and used and the results are compared with the results of the industry standard simulation tools. The tool is very fast as aimed and useful; it has been seen that it is enough fast and it gives the information to ease the actual design for a optimizer.
