Low power Advanced Encryption Standard (AES) implementation robust against side channel attacks

Abstract

As the people around the globe become increasingly connected to each other, the amount of information that flows becomes huge. Unfortunately, this vast information network is vulnerable to harmful attacks. Encryption is a strong tool that has been used for ages to act as a shield against these attacks. Among many algorithms utilized for encryption, one of the most popular is AES. AES is an approximately 20-year old algorithm that has been adopted by many organizations around the world to protect classified and unclassified data. In line with the trend of low power and secure implementations, the main intent of this thesis is to show a low-power AES implementation that is secure against power side-channel attacks. In the RTL, currently unused registers are kept constant to lower the power consumption. Choosing the LP ASIC process, using clock-gating, and preferring standard cells with higher threshold voltages enable more power saving. For the side-channel attack resistance, obfuscating and pipelining are employed. The obfuscating disguises the relation between the processed bits and the power consumption by modifying the processed information. On the other hand, the pipelining mixes power consumption related to different inputs with each other. The different versions of AES implementations are processed through FPGA and TSMC 65 nm ASIC flow to compare with each other. After the power traces are collected and analyzed by ChipWhisperer the side-channel attack resistance is evaluated. The effects of the obfuscating and pipelining in increasing attack resistance are proven after predicting key bytes from power traces stemming from thousands of random inputs. The area, power overheads in return for increased attack resistance are detected.