Multi-dimensional yield-aware optimization of the analog and heterogeneous circuits

Abstract

Even though the design of digital circuits is well supported by several CAD tools, this is not the case for analog circuits and MEMS where the design is typically hand-crafted by expert designers. Several tools have been implemented for trade-off exploration in analog circuits; however, yield-optimization is a hot and vital topic considering that process variations have deteriorated along with the feature sizes scaling down; hence, physical variations originating from manufacturing process have a huge impact on yield. Therefore, efficient yield-aware optimization methodologies for analog ICs are needed. MEMS design, on the other hand, requires a lot of expert knowledge, which implies long design times and increased cost due to this physical heterogeneity. The approach followed by the industry, based on composing separately designed sensors and read-out circuitry, has several issues such as inappropriate partitioning of system specifications or potential violation of system level constraints during the coupling process of the these devices. Hence, design methodologies which can obtain globally optimal MEMS by performing co-optimization of the sensor and the circuit are needed. This study is mainly focused on developing and implementing novel and generic design methodologies for multi-objective yield-aware optimization of analog circuits and MEMS. A novel yield optimization technique has been proposed and compared with the existing approaches and has provided very promising results for yield-aware Pareto Front generation. Besides the work conducted for yield-aware optimization, co-optimization of MEMS and analog circuits has been performed for the first time by jointly optimizing a mechanical accelerometer sensor and an electronic read-out circuitry. The implemented yield-aware optimization techniques have been integrated into the co-optimization loop to enable yield-aware multi-objective optimization of MEMS.