Error mitigation in next generation Nand flash memories

Abstract

The rapid developments and deployments in the global market of digital con sumer electronics in the last decade have stimulated the universal research on the dig ital storage technologies. NAND flash memory, fabricated based on the floating gate transistor cells, has become the ubiquitous storage technology, dominating the market at tens of billion dollars annually, due to its advantageous properties including very fast operation, low cost, significant scalability potentials, and low power consumption. However due to its complex structure, flash memory suffers from several complicated non-stationary error sources, namely inter-cell interference, retention error, and ran dom telegraph noise, which degrade its reliability and integrity. Recent advances in the next generation flash memories aiming to fabricate smaller and denser cells, specifically with introduction of multi-level cell technology capable of storing more than one bit of data per cell, result in amplified error sources, which critically limit the lifespan of the device. In this dissertation, error sources are analyzed and an accurate statistical model for the erroneously sensed threshold voltage of 2-level cells is derived, which enables us to compute the error rates of the flash memory channel in closed-form ex pressions. Furthermore, a novel two-dimensional equalization technique is proposed to mitigate the effect of the channel induced inter-cell interference. Derived expression are later extended to general cases, where the number of storage levels and interferers can arbitrarily be chosen. Finally, a novel machine learning based approach, based on both unsupervised and supervised learning mechanisms, is proposed, which can potentially tackle the non-stationarity of the channel to mitigate the corresponding error rates.