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Standard cell all-digital phase locked loop design, analysis and high-level synthesis

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dc.contributor Ph.D. Program in Electrical and Electronic Engineering.
dc.contributor.advisor Dündar, Günhan,
dc.contributor.author Balcıoğlu, Yalçın.
dc.date.accessioned 2023-03-16T10:25:15Z
dc.date.available 2023-03-16T10:25:15Z
dc.date.issued 2016.
dc.identifier.other EE 2016 B36 PhD
dc.identifier.uri http://digitalarchive.boun.edu.tr/handle/123456789/13134
dc.description.abstract This thesis presents a new quantization noise suppression method for a timeto- digital Converter (TDC) and proposes an all-digital phase locked loop (ADPLL) architecture using only standard cell logic gates. Using new multiple input multiple output (MIMO) quantization noise suppression method provides an order of p 2 improvement in TDC resolution with parallel TDC channels. Suppressed noise in TDC allows the ADPLL achieve superior jitter performance in both theoretical predictions and simulation results. In order to allow fast portability between process nodes, ease of modi cation, and provide exibility, ADPLL architecture is designed completely in register transfer level (RTL) intensive Verilog code and the implementation is synthesized in order to obtain nal microelectronic design schematics. In comparison to similar work in literature, designed ADPLL achieves superior long term jitter with comparable area and power consumption. Furthermore, we present a new tool called CellPLL that provides a complete design, analysis, and high-level synthesis (HLS) ow for all-digital phase locked loops (ADPLL). CellPLL uses a methodology for direct design of transfer functions given a set of speci cations by the user. In order to analyze the estimated phase noise of each design, a new phase domain model of ADPLL is incorporated. For automatic design implementation, a new HLS engine with a library parser and ADPLL realization template is used. The ow is applied for four di erent cases and the results match circuit level simulation results. CellPLL successfully generates ADPLL designs and provides ability to move between production processes.
dc.format.extent 30 cm.
dc.publisher Thesis (Ph.D.) - Bogazici University. Institute for Graduate Studies in Science and Engineering, 2016.
dc.subject.lcsh Phase-locked loops.
dc.subject.lcsh Phase-locked loops -- Design and construction.
dc.title Standard cell all-digital phase locked loop design, analysis and high-level synthesis
dc.format.pages xvi, 101 leaves ;


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