Standard cell all-digital phase locked loop design, analysis and high-level synthesis

Abstract

This thesis presents a new quantization noise suppression method for a timeto- digital Converter (TDC) and proposes an all-digital phase locked loop (ADPLL) architecture using only standard cell logic gates. Using new multiple input multiple output (MIMO) quantization noise suppression method provides an order of p 2 improvement in TDC resolution with parallel TDC channels. Suppressed noise in TDC allows the ADPLL achieve superior jitter performance in both theoretical predictions and simulation results. In order to allow fast portability between process nodes, ease of modi cation, and provide exibility, ADPLL architecture is designed completely in register transfer level (RTL) intensive Verilog code and the implementation is synthesized in order to obtain nal microelectronic design schematics. In comparison to similar work in literature, designed ADPLL achieves superior long term jitter with comparable area and power consumption. Furthermore, we present a new tool called CellPLL that provides a complete design, analysis, and high-level synthesis (HLS) ow for all-digital phase locked loops (ADPLL). CellPLL uses a methodology for direct design of transfer functions given a set of speci cations by the user. In order to analyze the estimated phase noise of each design, a new phase domain model of ADPLL is incorporated. For automatic design implementation, a new HLS engine with a library parser and ADPLL realization template is used. The ow is applied for four di erent cases and the results match circuit level simulation results. CellPLL successfully generates ADPLL designs and provides ability to move between production processes.