Enhanced layout-aware circuit / ststem synthesis

Abstract

This thesis presents the layout description script (LDS) which is suitable to be used within a template synthesizing layout aware circuit synthesis loop. LDS is a hybrid programming language supporting both sequential and constraint programming capabilities. Through constraint programming, representations used in the layout optimizers may be converted to LDS which enables the integration of LDS with layout optimizers. The language allows to code not only static devices but also parametrized device generators. LDS is compared with available layout representations and code samples are given to highlight the superiority of LDS over sequential programming. An integrated development environment to code LDS, capable of keyword highlighting and syntax checking, is built and some screen shots are shared. A tool is coded to extract an LDS template from an expert drawn layout and sample templates and their instances are shown. A sequential convex programming based methodology is developed and used to minimize the layout area, which is shown to be a convex function of the layout width and height under realistic assumption. Thus, the area of an LDS template may be e ciently minimized which increases the exibility of an LDS template.