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Asynchronous sigma-delta analog to digital converters

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dc.contributor Ph.D. Program in Electrical and Electronic Engineering.
dc.contributor.advisor Cerid, Ömer.
dc.contributor.author Kayaaltı, Balkır.
dc.date.accessioned 2023-03-16T10:25:10Z
dc.date.available 2023-03-16T10:25:10Z
dc.date.issued 2015.
dc.identifier.other EE 2015 K38 PhD
dc.identifier.uri http://digitalarchive.boun.edu.tr/handle/123456789/13122
dc.description.abstract Analog to digital conversion is the process of translating analog real world signals to their corresponding binary encoded form which digital devices need. Among the examples for analog signal sources storage devices like harddisks and sensor devices can be given. Analog to digital converters are key components that make this translation. A specific topology can be selected according to its achievable number of bits, speed, power and according to its area of usage. Sigma-delta analog to digital conversion is a popular type which can be used in applications where high resolution with moderate bandwidth is desired. High resolutions are achieved by the inherent noise suppression by the loop filter. Oversampling, which corresponds to the sampling of the input signal with a higher rate than that of the regular Nyquist rate is their other advantage. This process pushes the quantization noise away from the baseband, and thereby higher signal to noise ratios are achieved. There are mainly two sub-types of sigma delta converters. The first, is the discrete time version which uses discrete time signals and components. The second is the continuous time version which uses entire continuous time signals and components except the quantizer and the digital to analog converter (DAC) in the feedback. These two types are both clocked with an external clock signal, so the output is synchronous i.e. synchronized with a clock. Designing a new type of the circuit which does not use an external clock; but instead using the self oscillation created in the loop can be a an alternative third type. This type of the converter will not use sampling inside the loop, so clock jitter due to the sampling can be eliminated , where usually a high frequency signal is sampled. If the sampling is done with a lower frequency, effect of the clock jitter can be reduced. This thesis is about the theory of such converters and their design procedure with a real circuit implementation.
dc.format.extent 30cm.
dc.publisher Thesis (Ph.D.)-Bogazici University. Institute for Graduate Studies in Science and Engineering, 2015.
dc.subject.lcsh Analog-to-digital converters.
dc.subject.lcsh Asynchronous circuits.
dc.subject.lcsh Synchronous circuits.
dc.title Asynchronous sigma-delta analog to digital converters
dc.format.pages xvii, 87 leaves ;


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