Current-model CMOS sequential multiple-valued logic circuits

Abstract

The use of circuits with more than two logic levels, named as Multiple-Valued Logic (MVL) circuits, have a potential for reducing chip area consumed by interconnection wiring and functional units in Very-Large Scale Integration (VLSI). Many logical and arithmetic functions have been shown to be more efficiently implemented with multiple-valued logic in terms of number of operations, gates, transistor count and signal lines etc. However, in spite of their potential advantages, developments in multi-valued systems are not satisfactory. It is still a complicated task to design a system for processing a signal in a multi-valued manner despite considerable effort. Multi-valued logic circuits can be designed in current mode or voltage mode. Due to the limited supply voltages, higher radices could not be obtained using voltage mode circuits. On the other hand, current mode circuits have the advantages of current scaling, copying and sign changing with a simple current mirror, but unlike binary logic circuits, they are not self-restored. In this study, current-mode sequential logic circuits are designed and analyzed. Multiple-valued counterparts of the well-known flip-flop structures are discussed and a new type of flip-flop circuit, named AB, is proposed. The proposed circuit is used in various counter and random sequential circuit designs. Circuit schematics and simulation results are presented. In addition, a multiple-valued and binary counter designs that are using D-type flip-flops (the only flip-flop that has the same output equations for both MVL and binary) are compared in terms of various VLSI design criteria.