Alternative arithmetic structures using redundant numbers and multi-valued circuit techniques

Abstract

Arithmetic circuits play a crucial role in VLSI technology. Arithmetic blocks are usually the most power consuming parts in a system since the switching activity is quite high. Alternative arithmetic implementations can be a solution to reduce power consumption and to increase the performance of the whole system. Static CMOS digital design has robust working performance, where logic levels are kept at the two extremes, either the ground voltage or supply voltage. However, the voltage excursion between the supply voltage and ground at all nodes causes excessive power dissipation. This condition also generates noise over the whole circuitry, which is not desirable especially in mixed signal designs. Current-mode digital design techniques can be a solution for this issue especially whenever the switching activity is high. In the first part of the thesis, alternative current-mode arithmetic structures are built focusing on multi-valued circuits. Together with multi-valued logic implementations, signed-digit numbers and redundant number systems are also analyzed. The design issues of multi-valued circuits are discussed and novel building blocks for multi-operand addition are developed. In the second part of the thesis, redundant arithmetic schemes for new generation reconfigurable systems are also analyzed. These techniques proposed here can be implemented efficiently by using recently introduced 6-input look-up table based field programmable gate array (FPGA) systems. A redundant double carry-save mode addition technique is proposed for the new generation FPGA devices. Using the proposed technique, efficient multiply-accumulate operations and finite impulse response filter structures for reconfigurable systems are developed.