Circuit level analog design automation

Abstract

This thesis presents a simulation-based analog circuit synthesis methodology, its integration with system and layout level analog synthesis tools, and synthesis examples that were performed to validate the usefulness of the methodology. Simulation-based approach is preferred so that the synthesizer, SACSES, is topology independent. Instead of using a commercially available simulator, an accelerated simulator, SPASE, is implemented. SPASE has various acceleration mechanisms for DC, AC and noise simulation, detailed in the thesis. The search algorithm used is an ES algorithm modified so as to use Metropolis criterion as the selection method. By adding hill-climbing capability similar to simulated annealing, this modification provides a proper balance between local and global search and eliminates the premature convergence problem of GA and ES-based algorithms. Designer effort is minimized with the automated determination and self-evolution of search parameters. Smooth penalty mechanisms for biasing constraints are proposed and embedded in the algorithm. Yield-aware synthesis is performed by utilizing piecewise cubic Hermite splines for response surface modeling. A hierarchical synthesis structure is proposed for integrating SACSES with system level synthesis tools. The hierarchical scheme eliminates the need for extra tools to link levels. SACSES and the layout level synthesis tool is integrated with a feedback loop, by which the e®ects of layout parasitics on circuit performance are minimized.