Automatic test pattern generation for digital IC's and implementation of a programmable stimulus generator

Abstract

In this thesis work, two different topics are studied in order to perform a complete digital integrated circuit (lC) testing system, except an output analyzer. These topics can be separated as development of an automatic test pattern generation (ATPG) software for digital ICs and implementation of a programmable stimulus generator. A fault oriented and deterministic ATPG tool is developed running on SUNTM Sparc workstations. This tool is capable of generating test patterns, using a functional description of the IC under test, and a specific fault model which is called single stuck faults, for combinational circuits. This tool and similar tools which were developed in Virginia Polytechnic & State University are plugged to each other via a user interface to perform a ready to use complete test generator and fault simulator system for both combinational and sequential circuits. During the implementation of our tool, a recursive version of a path sensitization algorithm, named "fan-out-oriented (FAN) test generation" is used with some modifications. On the other hand, a 32 bit stimulus generator is implemented which is controlled by a 68000 microprocessor based system. This generator is capable of running up to 125 MHz. clock rates and has an interface to any PC via RS-232 serial communication protocol standards. Test vectors generated from our ATPG tool, can be downloaded to the stimulus generator in order to apply these vectors physically to the circuit under test at real operational clock rates. The implementation details, necessary theoretical background information for both topics and the analysis of the performance achieved are presented in this thesis.