Approximate processor design with RISC-V ISA

Abstract

With the rise of the Internet of Things (IoT), low-cost resource-constrained devices have to be more capable than traditional embedded systems, which operate on stringent power budgets. To add new capabilities such as learning, power consumption planning has to be revised. Approximate computing is a promising paradigm for reducing power consumption at the expense of inaccuracy introduced to the computations. In this thesis, we propose a processor with approximate processing functionality for resource-constrained IoT devices. A microprocessor with a dual-datapath mechanism is described in C++ and synthesized with a High-Level Synthesis (HLS) tool. A standard datapath exists for the parts of applications where the calculation should be exact. Additionally, an approximate datapath, which includes approximate computing features that will be more likely to exist in the next generation, low-cost, resourceconstrained, and learning IoT devices, is introduced. Coarse-grain control for setting the accuracy of approximate operations is adopted to reduce the number of control signals by grouping the bits so that they can be turned on-o simultaneously. The size of the operands of the approximate operators is dynamically adjusted at the data path without a ecting the performance. Based on these features, we propose new approximate adder and multiplier designs and integrate these blocks with a CPU, which bene ts from RISC-V ISA. Targeting machine learning applications such as classi cation and clustering, we have demonstrated that our processor reinforced with approximate operations can save power up to 23% for ASIC implementation while at least 90% top-1 accuracy is achieved on the trained models and test datasets.