Water - gated field effect transistor with integrated microfluidic channel

Abstract

This thesis establishes a novel fabrication method to integrate water-gated tran sistors with microfluidic channels using surface micromachining techniques. Transistors are designed and fabricated on 16 nm thick single crystalline silicon films of silicon on insulator (SOI) wafers. After fabrication, ID vs VDS characteristic is tested to prove that device is operational. To fabricate the device, thin film silicon is patterned to create channel region of the transistor. Then, 200 nm thick aluminum is evaporated to form source and drain contacts. Thermal annealing is applied to establish ohmic contacts between silicon and aluminum of the source and drain electrodes. To cre ate microfluidic channel, device is covered with sacrificial photo-resist with standard lithography. To form the gate electrode, aluminum is thermally evaporated on top of sacrificial photoresist which is on channel region using shadow mask technique. After the device’s surface is activated with oxygen plasma, 5 mm thick PDMS is casted and cured. Reservoir holes and contacts are obtained by punching holes in those regions through PDMS layer. Finally, microfluidic channel is released by acetone injected in side reservoirs to remove photoresist. Device is tested after the microfluidic channel is filled with DI-water, which forms the electrical double layer on surface of the channel region to create gate capacitance which is necessary to operate the transistor. Transis tor’s characterization is made between 0 and -0.8 V which is the region water operates without any ionization. Maximum output current obtained is 900 µA with 60 W/L ratio and ON/OFF ratio of 22 with threshold voltage of -0.4 V.