Design of A 12-BIT 3 GS/s current steering DAC

Abstract

Even if digital circuits are ubiquitous thanks to the easier design and test automation, the real world is an analog place. DACs are the circuit blocks which allow converting the signals which are easily processed in digital domain to the analog domain. Local oscillators, arbitrary waveform generators and other modern communication systems utilize high speed DACs. Current steering DACs are the prevalent architectures for high-speed applications. Spectral purity of the DAC output is the main performance consideration and degraded by dynamic and static errors. In this thesis work a 12-bit 3 GS/s current steering DAC designed in 65nm CMOS process is presented. The design of the blocks in the DAC are examined through considering dynamic and static error mechanisms. Simulation results show that the DAC has SFDR up to 60 dB with the power consumption of 922 mW for typical process conditions and 3 GHz operating clock frequency. Besides, during measurements the DAC reaches SFDR up to 65 dB and has a power consumption of 830 mW. Finally, the active area of the DAC is 1 mm2.