An analog template router based on layout description script (LDS)

Abstract

Long design-test cycles in full-custom design process leads to high design costs in analog circuit design. The objective of design automation is to decrease the design cost and the time to market by reducing the time spent in the design process. Template-based tools have an advantage of requiring lower computational time by utilizing stored design knowledge. This property makes template based design techniques very appealing for some applications such as porting a design to di erent technologies or making minor changes on the design in the same technology. Unutulmaz et al. (2011) presented a declarative language to de ne layout templates for analog circuits, named Layout Description Script (LDS). In this study, a template router is proposed which outputs routing information for layout templates coded in LDS. The output of the router is exible routing information also coded in LDS. It is shown that the layout instances created from the output template with routing information can adapt itself to the changes in the dimensions of the circuit elements. Therefore, the template can be used by design automation tools in a closed optimization loop. The router proposed in this thesis di ers from the other routers by the nature of it's input and output. The input le holds the relative placement information of the circuit elements rather than providing xed coordinates in the layout. Likewise, the output le consists of relative positions of the interconnect and is self-adapting for the variations in dimensions of the circuit elements.