Low power continuous time sigma delta modulator and decimation filter design

Abstract

Sigma Delta analog to digital converters (ADC) are widely used in areas where high resolution is needed. Audio applications are one of these areas. Along with high resolution, reducing the power consumption of an ADC is a very significant design problem. A Sigma Delta ADC consists of two main blocks: analog modulator and digital decimation filter. Modulator utilizes oversampling and noise shaping processes in order to move noise to higher frequencies whereas the decimation filter down-samples the sampling frequency and eliminates redundant data which are result of the oversampling process. Concerning low power ADC design, most of the effort is being spent on analog part of the converter. The digital decimation filter can also consume as much power as the analog part. In this thesis, a low power Continuous Time Sigma Delta modulator for audio frequencies and a low power Decimation filter for discrete time Sigma Delta modulator intended for audio application are implemented. A 2nd order continuous time Sigma Delta modulator with an oversampling ratio of 128 is first designed in MATLAB, then the proper architecture is realized in Mentor Graphics schematically using 0.18 μm CMOS technology. Simple and easy to design structure is chosen for the modulator. Most of the power is consumed in operational amplifiers of integrators; therefore, operational amplifiers with low power consumption are designed. gm-C type integrators, which employ telescopic cascode amplifiers as gm unit, are utilized in the design. Power consumption of the modulator is found to be 9.82 μW. A decimation filter is designed for a low power discrete time Sigma Delta modulator intended for audio applications. The modulator has an oversampling ratio of 32, a signal bandwidth of 25 kHz and a sampling frequency of 1.6 MHz. The main goal of the design is to reduce the power consumption of the digital filter below that of the analog modulator. Multistage filter structure is employed in order to save area and power. The first stage of the 3-stage structure is Cascaded Integrator Comb Filter (CIC), the second and third stages are Half-Band (HB) and Finite Impulse Response (FIR) Filters respectively. Unlike conventional form, CIC filter is also implemented in three stages and non-recursive format such that it has FIR transfer function. HB filter coefficients are generated with MATLAB FDAtool which uses Parks McCellan Algorithm. FIR filter coefficients are generated with GAM algorithm which provides coefficients with minimum number of signed power of two (SPT) terms while keeping quantization word length as small as possible. Several low power digital design techniques are applied to filters in order to obtain a low power decimation filter. Filters are designed with MATLAB Simulink tool, realized with Verilog hardware design language (HDL) and synthesized with Synopsys Design Compiler (DC) tool using 0.18 μm CMOS technology. Measured power consumption of the Decimation filter is 7.24 μW under 1.8 V supply voltage, only half of the DT Sigma Delta analog modulator.