10-BIT 60 MS/s two-step flash ADC design

Abstract

Two step flash ADCs have widespread use in electronic circuits, since they can achieve decent resolutions in high speed applications. Their two step structure requires coordination of many analog blocks that is ensured by control signals. Generating and delivering these control signals as clock signals are as important as the design of the analog blocks. In this thesis analog design of a two-step flash ADC which is used as a test circuit for an automation tool that can synthesize the necessary clock signals is presented. The design procedures of the blocks in 10-bit 60 MS/s two step flash ADC are examined. The overall design is realized by using UMC 180nm technology. Finally the simulation results obtained by using Mentor Graphics tools and MATLAB are presented. The performance of the ADC is evaluated using ENOB as a figure of merit. Resolutions up to eight bits are attained in typical case simulations. Comparison with the literature is also made by using energy per conversion values.