Aging in CMOS circuits and circuit design robust to aging phenomena

Abstract

The subject of aging in CMOS circuits has been examined and some reliability simulations have been run for analog CMOS circuits in order to observe the e ects of this phenomenon on the reliability of CMOS circuits in this work. Electronic circuits also have a useful lifetime as everything in the nature. This time can be de ned as a regular period where the circuit is able to work properly and do its function accurately. Despite the fact that rapid advances in semiconductor technology brings many advantages, there are also some drawbacks. One of these negative consequences is reduction of reliability of circuits. Aging isn't a new trend for the CMOS circuits but, after the iteration of Moore's law which pushed the transistor channel length to under 180 nm, the subject of aging has been elevated from an academic exercise to a growing, and perhaps a detrimental concern which the foundries have focused on. In order to understand the physical mechanisms and create solutions to this phenomenon, reasons should be manifested clearly by both researchers and foundries. There are a number of physical failure mechanisms a ecting the reliability of a CMOS ASIC. Hot Carrier Injection (HCI), Negative Bias Temperature Instability (NBTI), Time Dependent Dielectric Breakdown (TDDB) and Electromigration are the most common failure mechanisms. The physical causes are investigated and a number of aging models of these mechanisms were discussed in the initial chapters. In addition to this theoretical study, three diverse CMOS Cross-Coupled Di erential LC Oscillators (NMOS, PMOS, and CMOS) were designed to observe the aging e ects on phase noise of each structure, reliability simulations were run for each structure, and the study is completed by evaluating all of these results.