Design of a power aware asynchronous AES circuit

Abstract

As the security and privacy awareness continuously arise, cryptographic services such as data con dentiality, integrity, authentication, and non-repudiation become an essential and indispensable part of digital systems and communication networks. Most of the digital circuits rely on synchronous design approach where a single system clock de nes the timing of the communication between digital components. However, with the increasing complexity of digital circuits, it is becoming more and more di cult (and energy ine cient) to provide a global clock signal across the whole circuit synchronously. Hence, asynchronous designs emerge as a low power alternative in designing power aware systems urged in cryptographic engineering. In this thesis, it is managed to realize a power aware asynchronous AES (Advanced Encryption Standard) circuit that consumes much less power than similar synchronous implementations. While Balsa is used as a framework to synthesize asynchronous circuits, all low power measurements are carried on Xilinx FPGA families for a fair comparison with the existing literature.