High performance adaptive sigma delta modulator designs

Abstract

Improvements in VLSI technology enabled data converters with increased speed. When compared to conventional converters, sigma delta modulators have a higher sampling speed for resolution; and they are less sensitive to analog circuit non-idealities. Despite their advantages, sigma delta converters have their own challenges . As the sampling frequency increases the second order effects such as parasitic poles in the loop filter or delay of the quantizer affect the performance of the modulator. Another drawback of the SD modulator is the saturation level limitation of the integrator which has a degradation effect on resolution. To overcome these problems, architectural or circuit level solutions should be studied. In this thesis, saturation problem of the integrator block will be discussed. Saturation problem of the Operational Amplifier that is used in the integrator block affects the dynamic input signal range of Sigma-Delta modulators. This limitation results in inaccurate outputs of the modulator. Consequently, the saturation effect should be eliminated in such a way that the integrator block of the modulator should not enter the saturated region. The analysis is carried out in two different levels. First, analysis is carried out at behavioral level to see the performance of the modulator excluding the transistor nonidealities. In this thesis, an adaptive modulator structure is proposed. Also, the analysis with this adaptive architecture is done with behavioral models to see the feasibility of the proposed structure before implementing it in transistor level. The adaptive architecture includes an additional logic circuitry. This logic circuitry is triggered whenever the output of the integrator is getting close to the saturation levels and connects an extra capacitance to the feedback of the integrator. By the help of this extra capacitance, the gain of the integrator is decreased dependent on the size of this capacitor. The proposed adaptive architecture is tested with behaviorally defined components and the result turned out to be that the adaptive modulator has a better SNR performance with respect to applied input signal range. After verifying the improvement in performance with behavioral level analysis, implementation is made with transistor level components using 0.35 um AMS technology. All elements that compose the modulator are designed at transistor level and tested individually. These transistor level designed elements are inserted to the modulator one by one. Adaptive and non-adaptive architecture behavioral level analysis are repeated with transistor level elements. Finally, the analysis results of the analysis done at transistor level also supports that adaptive architecture has a better SNR performance with respect to dynamic input signal range compared to non-adaptive architecture. Thus, the proposed adaptive modulator presents an alternative solution to the resolution degradation.