Analog layout synthesizer for a parasitic aware design loop

Abstract

Analog design automation is being studied for a couple of decades and many researchers developed their own tools. However, there are no standards for these tools. The work done in this M.S. thesis aims to define standard interfaces for layout automation tools, making the integration of different tools possible. In addition to these interfaces, an interface for a layout database is defined. This interface is designed to hold any kind of layout structure and to cooperate with any kind of layout tool. Additionally, implementations for these interfaces are done. A floor-planner tool, a device generator, a fast database and a simple router are implemented in Java. The implemented tools are combined and a template based layout synthesizer is constructed. This layout synthesizer requires templates files coded in Java. Implementing the floor-planner, a new floor-plan representation and a new inequality solver are developed and used. Moreover, a novel synthesis loop is defined. In this synthesis strategy, contrary to the old synthesis approaches, the effects of the parasitic are considered in the synthesis loop. The layout synthesizer implemented in this thesis is preferable in this novel synthesis loop, due to the very short running time.