High performance 16 bit multiplier design using mos current mode logic

Abstract

In this work, MOS Current Mode Logic (MCML) is determined for low power and high speed applications. A small MCML cell library is developed and optimized for several different performance requirements. These requirements are voltage swing, voltage gain and current. The cells are then applied to the implementation of a 16 bit signed multiplier . In the literature, there are only two 8 bit MCML multipliers [12] [13] . We couldn’t find any 16 bit MCML multiplier in the literature. Modified radix 4 booth encoding is used to reduce the number of partial products by half for the multiplier architecture. Also, Wallace tree structure is used to sum the partial products in reduced time. In the Wallace tree, only full adders and half adders are used. For the completion adder, a fast and low power 32 bit hybrid adder is used. Design is done in the 0.18μm UMC technology. A 16 bit non-pipelined MCML signed multiplier is designed and tested with 4 different reference voltages. The first one works at 800 MHz, consumes 55 mW. The second one works at 600 MHz, consumes 37mW. The third one works at 400 MHz, consumes 27mW. The last one works at 250 MHz, consumes 16 mW. The power of the third one is 25 % less than the CMOS multiplier with equivalent operating frequency, given in reference [14]. Also the speed of the second one is 50 % faster than the CMOS multiplier with equivalent power, given in reference [14]. The power supply current spike is only 4 % of the nominal current and the multiplier consists of 7268 transistors. The CMOS multiplier given in reference [14] consists of 13444 transistors.