High performance adaptive sigma delta modulator designs

Abstract

In this work two different solutions to the saturation problem of the integrator building block of Sigma Delta modulators are presented. Saturation causes an error that limits the dynamic input range of the Sigma Delta A/D converters. Therefore, integrator must be prevented from entering saturation in order to get correct and meaningful data out of the modulator. In the first proposed solution, when the output voltage of the integrator reaches the edge of saturation, designed circuit properly adapts the gain of the integrator to prevent it from clipping by simply adding an extra capacitor to the feedback path of the opamp and eventually decreases the summing step size of the integrator. Conversely, when the integrator output moves away from the saturation region, the added capacitor is removed from the circuit. This process is accomplished with help of a control circuit consisting of Schmitt Triggers and logic circuits. Second method tries to solve the problem by using a non-uniform multi-bit quantizer architecture. One bit SD modulators are more resistant to the clipping effect of the saturation compared to multi-bit architectures. However it is also known that multi-bit SD architectures have much better SNR properties than one bit modulators. The proposed circuit tries to take advantage of both architectures by acting like a multi-bit modulator when output of the integrator is far away from saturation region and like a one bit modulator when the circuit enters into saturation.