Analog CMOS implementation of neuro-fuzzy systems

Abstract

In this thesis, a novel neuro-fuzzy system presented and implemented in analog CMOS. The system is based on the fact that a rule in a zero order TSK fuzzy system can be represented as an area on an input space which is created by a neural network. If the rule output values of the fuzzy system are assigned to the corresponding areas and additionally, if the neuron threshold values and the weights of the neural network are selected suitably, the fuzzy system can be mapped on the neural network. Implemented system consists of five main blocks, area selection block, normalization block, weight assigning block and summing block. The blocks and their designs are introduced and additionally digital control units, which are used for determination of desired areas and values, are presented. Implemented chip works in current mode, while the inputs are taken as voltages and the output is taken as a current. SPICE and theoretical MATLAB simulations and example fuzzy rule mappings show that implemented chip architecture works accurately and it is able to evaluate eight million fuzzy rules per second. The maximum power dissipation of the chip is equal to 37 mW.