Digital filter design, error modeling and error correction in sigma-delta modulators

Abstract

Modern electronic systems that are used in computers, automotive, communication, etc., are mostly mixed-signal systems. To implement mixed-signal systems, it is necessary to convert analog signals into the digital domain with the help of analog to digital (A/D) converters. Sigma Delta ( ΣΔ ) Modulators also called Oversampling Converters have found widespread applications in many electronic systems because of their high speed, high resolution and low analog circuitry cost more than other A/D converters. Even though ΣΔ conversion is intrinsically less sensitive to non-idealities than other A/D conversion techniques, non-idealities in ΣΔ building blocks can directly limit the overall performance of these converters. To increase the performance, the non-idealities such as finite amplifier gain, reference voltage errors, component mismatches, charge injection errors etc., can be reduced in the analog domain by careful analog circuit design or in the digital domain by noise-cancellation and reduction blocks. In this thesis, it is aimed to perform the implementation of digital error correction and calibration algorithms for ΣΔ Converters in VHDL-AMS, an extension to VHDL standardized by IEEE. To achieve this, 1) Linear Least Mean Square (LMS) based digital filter, of which the coefficients are adaptively determined on-line to correct finite amplifier gain, component mismatch, reference voltage offset errors and 2) A novel dynamic element matching technique as a digital block that can be easily incorporated with any unit element DAC to correct DAC nonlinearity or reference voltage errors are implemented. The results of these error correction and calibration circuits are evaluated on 3-bit Second Order ΣΔ Converter and as a result significant SNR improvement is achieved.