Yet another simulation based sensitivity analysis tool for analog layout generation

Abstract

In this thesis, a high performance and flexible analysis tool is presented for computing the sensitivities of performance measures of analog integrated circuits to the parasitic effects that are introduced during layout synthesis and manufacturing. The proposed sensitivity analyzer YASAv2 is based on YASAv1 developed by Mehmet Selçuk Ataç which makes use of its own circuit simulators for computing values of performance measures. YASAv2 is a general purpose tool which can analyze any CMOS circuit provided in SPICE netlist format. YASAv2 supports LEVEL2, LEVEL3, and BSIM3 mosfet parameters. YASAv2 can carry out simplifications according to the computed sensitivity values and the performance specifications provided by the user, to get significant set of parasitic effects which have a critical impact on overall circuit performance. In YASAv2, a new AC analyzer, new parasitic set models, substrate coupling model and inductance as a circuit element are added. Like YASAv1, YASAv2 is coded in C++ using object-oriented programming method. A MFC interface is added for easy usage. It is aimed to integrate YASAv2 into performance driven analog layout synthesis tools (ALG).