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dc.contributor Graduate Program in Electrical and Electronic Engineering.
dc.contributor.advisor Dündar, Günhan, 1959- .
dc.contributor.author Yılmaz, Ender.
dc.date.accessioned 2023-03-16T10:16:50Z
dc.date.available 2023-03-16T10:16:50Z
dc.date.issued 2006.
dc.identifier.other EE 2006 Y55
dc.identifier.uri http://digitalarchive.boun.edu.tr/handle/123456789/12669
dc.description.abstract In this work an analog layout automation tool, ALGv3, is presented. ALGv3 is successor of ALGv2, which was also designed at Bogazici University. ALGv3 is composed of four parts; module generator, partitioner, placer and router. Module generator is capable of generating simple transistors as well as complex structures such as merged, interdigitized and common centroid transistors. Modules can be generated in a performance oriented manner. Parameters of modules that are extracted in the generator such as parasitic values, matching and aspect ratio values are combined in a cost function. This cost function is used to find the optimum generation parameters such as fold number or quad number for module generator. Transistors are partitioned into groups in order to ease the job of placer. Well known structures are recognized in the circuit and transistors of the same group are kept together in placement step. Router is not finished yet, the total currently routes the nodes, but these routes are not converted to actual layers.
dc.format.extent 30cm.
dc.publisher Thesis (M.S.)-Bogazici University. Institute for Graduate Studies in Science and Engineering, 2006.
dc.relation Includes appendices.
dc.relation Includes appendices.
dc.subject.lcsh Integrated circuits -- Very large scale integration.
dc.title Analog layout generation
dc.format.pages xiv, 89 leaves;


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