Analog layout generation

Abstract

In this work an analog layout automation tool, ALGv3, is presented. ALGv3 is successor of ALGv2, which was also designed at Bogazici University. ALGv3 is composed of four parts; module generator, partitioner, placer and router. Module generator is capable of generating simple transistors as well as complex structures such as merged, interdigitized and common centroid transistors. Modules can be generated in a performance oriented manner. Parameters of modules that are extracted in the generator such as parasitic values, matching and aspect ratio values are combined in a cost function. This cost function is used to find the optimum generation parameters such as fold number or quad number for module generator. Transistors are partitioned into groups in order to ease the job of placer. Well known structures are recognized in the circuit and transistors of the same group are kept together in placement step. Router is not finished yet, the total currently routes the nodes, but these routes are not converted to actual layers.