Power analysis and low power realization of digital filter structures

Abstract

Digital Filters are important for Digital Signal Processing (DSP) systems. They are widely used in image, speech processing, data transmission. Digital Filters can be used to reduce noise in the system, get information from the signal, etc. However, these filters consume high power even if they are made in a full custom fashion. The reason is the multiplications or divisions in the filters. The filters include large number of multipliers. However, if constant coefficients are used in the filter, multiplier operations can be represented by adders, subtractors and shift operations. By using Canonic Signed Digit (CSD) representation and making subexpression sharing on the coefficients, the number of adders in the multiplier which leads to less area and less power consumption. In this thesis, Finite Impulse Response (FIR) filter structures are studied. A different subexpression sharing algorithm is created to select appropriate subexpressions. Subexpressions are selected such a way that the adder depth is minimized. Minimizing adder depth caused few more adders compared to the other subexpression sharing algorithms. However, minimizing the adder depth minimizes the delay and glitches. In the algorithm, the minimum length subexpressions are selected first. Therefore, the full adders (FAs) used in the adders are reduced.