Analog design and optimization of PWL circuits used in fuzzy logic solutions

Abstract

Neural networks are widely used in all branches of life such as system identification, decision support and control where systems are designed to be working as human brain and make decisions like the way human beings do. Although neural networks describe much more precise solution surface, fuzzy logic is becoming more popular since complexity, trainability and especially hardware implementation of fuzzy logic is much easier. This work is concerned with the construction of fuzzy logic piecewise linear functions (PWL) that are used for solution surface approximation. Various combinations of CMOS current mirror circuits are used to realize PWL functions. There are several sources of errors in design of such functions. In order to simplify the optimization of these error calculations, PWL circuits are divided into smaller circuits which are assumed to be current mirrors in this work. Implementation error which is caused by deviation from the real solution surface and mismatch errors between current mirror transistors due to difference between threshold voltages (Vt), oxide capacitance (Cox), width and length of transistor values are considered as the main sources of errors. This work represents a computer aided tool for calculation of optimized W and L values of current mirror transistors for various values of reference current within a specified error to find the best transistor parameters for possible minimum power dissipation. Results are tested on several applications to verify that the results of the computer aided system presented in this work are matching with the simulation results. It has been seen that instead of designing and calculating PWL circuits manually, introduced optimization tool may well be used in such processes.