System level design of phase locked loops

Abstract

Phase Locked Loops (PLLs) are extensively used in microprocessors and digital signal processors for clock generation and as frequency synthesizers in RF communication systems for clock extraction and generation of a low phase noise local oscillator signal from on-chip voltage controlled oscillator (VCO). In this thesis, the analytical expressions for the system specifications of simple loop PLL architecture are derived and tested with VHDL-AMS simulations to develop an approach allowing the systematic design of PLLs. This approach allows the designer to maintain a grasp of the fundamentals using the coarse models at the early stage of the design and eventually to gain insight on the lower order effects by gradually increasing the level of detail as the design develops. The problem of noise analysis of PLLs is addressed in the presence of circuit white noise sources yielding the spectrum of the PLL output. Behavioral modeling of phase noise and jitter in PLLs with VHDL-AMS is implemented, and the correlation between the developed models and analytical noise analysis expressions is shown.