A general design methodology for embedded high speed A/D converters

Abstract

There are various types of analog-to-digital converters available in the literature. The fast and efficient data converter design automation systems gaining more and more interest. Although there are tools available for the synthesis of specific ADC architectures, there's need for development of the methods for the systematic selection of the topology. The first step in data converter design automation is the selection of the adequate architecture. This thesis proposes a methodology for the systematic selection of the topology. Different architectures have been modeled in this study. Using these models, the restrictions introduced have been calculated. These restrictions have been used for generating the specifications of the blocks of each topology. The optimization has been done for the specifications. Then, the library has been searched for an adequate block that satisfies the required specifications. If the methodology could not find a solution, the range of inputs have been swept. Then the area, the power and the speed performances have been calculated in order to find the optimum topology. The methodology for optimum topology selection has been realized. The results of the methodology were tested with the previous work. The results were similar as expected but models need further improvement for higher accuracy.