RH (+): the model for high-level embedded system design on run-time reconfigurable hardware

Abstract

The process of embedded system design on recon gurable architectures needs smart solutions to reduce the cost of development life-cycle and to use resources ef- ciently at run-time. However, the current solutions (SystemC/xtUML), which are extended from the traditional languages (C++/UML), are insu cient for that. Ine ciency occurs due to: detailed operator de nition requirement, forcing user to pay attention low-level design problems at higher levels, complex hardware abstraction procedures, misguiding user during mapping software to hardware, not permitting user to de ne constraints at the level having software intermediate representation, and outputs lacking of performance from high levels to lower levels. Therefore, the traditional methods must only be used for what they are designed, in order to bene t from them e ciently. In this thesis, we propose: (1) RH(+); a brand new high level embedded system design model for run-time recon gurable architectures, solving the aforementioned ine ciency problems, (2) LRH(+); a brand new design language which is not extended from any traditional languages, (3) FRH(+); the framework meeting RH(+) requirements. In our work, we have the tools for developing board support package, de ning miscellaneous operators, generating graphs for user interactions, pro ling, resource scheduling, nding possible paths with their execution delays, and run-time emulation of recon gurable hardware.