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Dijital Arşivi

An embedded RISC-V with fast modular multiplication

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dc.contributor Graduate Program in Computer Engineering.
dc.contributor.advisor Yurdakul, Arda.
dc.contributor.author Irmak, Ömer Faruk.
dc.date.accessioned 2023-03-16T10:04:44Z
dc.date.available 2023-03-16T10:04:44Z
dc.date.issued 2020.
dc.identifier.other CMPE 2020 I76
dc.identifier.uri http://digitalarchive.boun.edu.tr/handle/123456789/12432
dc.description.abstract While one of the biggest enabling factors of Internet of Things growth is cheap and capable hardware, maybe the biggest concern is privacy and security. Encryption and authentication need big power budgets, which battery-operated IoT end-nodes do not have. Hardware accelerators designed for specific cryptographic operations provide little to no flexibility for future updates. Custom instruction solutions are smaller in area and provide more flexibility for new methods to be implemented. One drawback of custom instructions is that the processor has to wait for the operation to finish. Eventually, the response time of the device to real-time events gets longer. In this work, we propose a processor with an extended custom instruction for modular multiplication, which blocks the processor, typically, two cycles for any size of modular multiplication. We adopted embedded and compressed extensions of RISC-V for our proof-of-concept CPU. Our design is benchmarked on recent cryptographic algorithms in the field of elliptic-curve cryptography. Our CPU with 128-bit modular multiplication operates at 136MHz on ASIC and 81MHz on FPGA. It achieves up to 13x speed up over software implementations while reducing overall power consumption by up to 95% with 41% average area overhead over our base architecture.
dc.format.extent 30 cm.
dc.publisher Thesis (M.S.) - Bogazici University. Institute for Graduate Studies in Science and Engineering, 2020.
dc.subject.lcsh Quantum computers.
dc.title An embedded RISC-V with fast modular multiplication
dc.format.pages 56 leaves ;


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