A simulation model for bus based shared memory multiprocessor systems

Abstract

Simulation modelling is one of the most common methods to predict the performance of multiprocessor computer systems. In this study, a new simulation model is developed and a simulator based on this model is implemented to predict the performance of the bus based shared memory multiprocessor systems. The main inputs of the simulator are representation of the architecture and workload parameters. There are several proposed algorithms to process these inputs, including path finding, mailbox location, and memory units clustering algorithms. A number of protocols are also devised and implemented in the simulator. The verification and validation studies are very important for a simulator. The verification study is realised by the help of several analytical models, which are available in the literature. The validation is realised by the performance results of the TOMP prototype. In the last part of the thesis, several sample runs are provided to analyse and compare certain architectures under various workload conditions.